Digital signal processing common mistakes

Common mistakes

• Misidentifying a NAND gate as an AND gate

  Students often think a NAND gate symbol is the same as an AND gate because both have a similar shape, but a NAND gate has a small circle at the output.

  Fix itRemember that a NAND gate is an AND gate followed by a NOT gate. The symbol is the AND gate shape with a small circle (inversion bubble) at the output. Check the presence of the circle to distinguish it from a plain AND gate.

• Missing input combinations

  Students often omit one or more input combinations when constructing a truth table, resulting in an incomplete table.

  Fix itRule: A truth table must list all 2^n combinations of the n inputs. Substitution: For a 2‑input gate, the combinations are 00, 01, 10, 11. Working: Enumerate each pair: (0,0), (0,1), (1,0), (1,1) and calculate the output for each. Answer: The table contains 4 rows. Conclusion: Including all combinations ensures the logic circuit is fully described.

• Confusing XOR and XNOR expressions

  Students often write the Boolean expression for an XOR gate as A·B + ¬A·¬B, which actually represents XNOR.

  Fix itThe XOR gate outputs 1 when exactly one input is 1. The correct Boolean expression is A·¬B + ¬A·B. To verify, substitute the four possible input combinations: - A=0, B=0: A·¬B + ¬A·B = 0·1 + 1·0 = 0 - A=0, B=1: 0·0 + 1·1 = 1 - A=1, B=0: 1·1 + 0·0 = 1 - A=1, B=1: 1·0 + 0·1 = 0 These results match the XOR truth table. Thus the correct expression is A·¬B + ¬A·B, not A·B + ¬A·¬B. The latter is the XNOR expression.

• Assuming memory in combinational circuits

  Students often think that a combinational logic circuit can remember previous inputs or have state.

  Fix itExplain that combinational circuits have no memory; outputs depend only on current inputs; use sequential elements such as flip‑flops or latches for state.

• Latch vs Flip‑Flop Clock Sensitivity

  Students often think that a latch and a flip‑flop behave the same, assuming both change state only when the clock is high.

  Fix itExplain that a latch is level‑sensitive: it holds its output while the enable (clock) is active and can change state at any time during that level. A flip‑flop is edge‑triggered: it changes state only on a specific clock transition (rising or falling edge). Clarify that the latch can be transparent when the clock is high, whereas the flip‑flop only samples the input at the clock edge.

• Timing diagram of D flip‑flop

  Assuming the output changes immediately with the clock signal, ignoring the edge‑triggered nature of the flip‑flop.

  Fix itEvidence: In a typical D‑flip‑flop timing diagram the output Q remains constant until a clock edge occurs, then it takes the value of the D input present at that instant. Interpretation: The flip‑flop samples the D input only on the specified clock edge (rising or falling) and holds the previous output until the next edge. Implication: Students must identify the clock edge in the diagram and recognise that Q will not change until that edge, even if D changes earlier. Conclusion: To interpret the diagram correctly, look for the clock edge, note the D value at that moment, and understand that Q will update only at that edge, remaining unchanged otherwise.

• Clock Signal Synchronisation

  Students often think the clock signal only tells when the output changes, ignoring that it synchronises all sequential elements.

  Fix itFormula/rule: Clock edge triggers state change. Substitution: At each rising edge, the sequential element samples its input. Working: The clock ensures all elements update simultaneously, preventing race conditions. Answer: The clock synchronises state changes across the circuit. Units/conclusion: No units; conclusion: The clock provides timing and synchronisation for sequential logic.

• Astable Circuit Misconception

  Students often think an astable circuit has a stable state that holds a logic level until triggered.

  Fix itAn astable circuit has no stable state; it continuously oscillates between high and low, producing a square wave used for clock generation.

• Incorrect period formula for 555 astable

  Students often use T = 2RC instead of the correct T = 2RC ln(2) for a 555 timer astable circuit, leading to an overestimation of the period.

  Fix itUse the correct formula T = 2RC ln(2) (≈1.386RC) and substitute the correct resistor and capacitor values.

• Duty cycle confusion

  Students often think duty cycle is the ratio of high time to low time, rather than the proportion of the total period during which the signal is high.

  Fix itExplain that duty cycle is the fraction of the period that the output is high, expressed as a percentage: duty cycle (%) = (high time ÷ period) × 100. Emphasise that it is a dimensionless ratio of time, not a comparison of high to low times.