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In the timing diagram for a D flip‑flop, the clock rises at 10 µs and the D input is 1 just before the rise. When does the Q output change?

Try the question, check the answer, then read the explanation to understand the curriculum point.

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MCQ

Type

practice

Style

Topic

Digital signal processing

Exam-style question

Try this first

In the timing diagram for a D flip‑flop, the clock rises at 10 µs and the D input is 1 just before the rise. When does the Q output change?.

  1. A.Immediately at the clock rise
  2. B.At 10 µs, after the clock has finished rising
  3. C.At 20 µs, one clock period later
  4. D.It never changes

Model answer

What a good answer should say

  • Immediately at the clock rise

Explanation

Why this works

Evidence: The diagram shows the clock rising at 10 µs and D=1 at that instant. Interpretation: A D flip‑flop captures the D value on the rising edge.

Implication: Q will adopt the value of D immediately after the edge. Conclusion: The correct answer is that Q changes immediately at the clock rise.

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