Exam-style question
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In a timing diagram for a cross‑coupled NAND SR latch, both S and R inputs are high simultaneously. What state does the latch enter?.
- A.Q=0 and Q̅=1
- B.Q=1 and Q̅=0
- C.Both outputs become 1
- D.Both outputs become 0
Model answer
What a good answer should say
- Both outputs become 1
Explanation
Why this works
Evidence: The diagram shows S=1 and R=1 at the same time. Interpretation: For NAND latches, high inputs force both outputs to high.
Implication: The latch enters an invalid state where both outputs are 1. Conclusion: The correct answer is that both outputs become 1.
Common mistake
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