Exam-style question
Try this first
A D latch is transparent when the clock is high. According to the timing diagram, during which interval is the latch transparent?.
- A.From 0 µs to 5 µs
- B.From 5 µs to 10 µs
- C.From 10 µs to 15 µs
- D.From 15 µs to 20 µs
Model answer
What a good answer should say
- From 5 µs to 10 µs
Explanation
Why this works
Evidence: The diagram shows the clock high between 5 µs and 10 µs. Interpretation: A D latch passes the D input to Q only while the clock is high.
Implication: The latch is transparent during that interval. Conclusion: The correct answer is that the latch is transparent from 5 µs to 10 µs.
Common mistake
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