Structure and role of the processor and its components revision notes

Main processor components

The arithmetic logic unit (ALU) performs arithmetic and logical operations. These include addition, subtraction and logical bitwise operations such as AND, OR, NOT and XOR. It can also perform logical shifts to the left or right. The control unit (CU) controls and coordinates processor activity, including the stages of the Fetch-Execute cycle. The clock provides regular timing signals so that processor operations occur in a coordinated sequence.

General-purpose registers are small, fast storage locations used by the processor for values and intermediate data. Dedicated registers have specific roles:

• The program counter (PC) holds the address of the next instruction to be fetched.
• The current instruction register (CIR) holds the instruction currently being decoded or executed.
• The memory address register (MAR) holds the address in memory that is being accessed.
• The memory buffer register (MBR) holds data being transferred to or from memory, including an instruction being fetched.
• The status register stores information about the result or state of an operation.

Fetch-Execute cycle

During fetch, the address in the PC is copied to the MAR. The instruction at that address is obtained from memory and placed in the MBR. The instruction is copied to the CIR, and the PC is updated so that it refers to the next instruction. During decode, the control unit interprets the instruction in the CIR, identifying the operation and the operand information. During execute, the required operation is carried out, using the ALU, registers or memory as appropriate. The cycle repeats until a halt operation is executed.

Instructions and addressing modes

A processor has a processor-specific instruction set: the collection of machine-code operations it can interpret. An instruction consists of an opcode and one or more operands. An operand may be a value, a memory address or a register. In the simple model, the bits allocated to the opcode also define the addressing mode.

With immediate addressing, the operand is the datum itself. For example, LOAD #7 means load the value 7. With direct addressing, the operand is the address of the datum. For example, LOAD 7 means load the value stored at address 7. An address can refer to main memory or a register, depending on the context.

If 4 bits are allocated to the opcode and 4 bits to the operand, an instruction is 8 bits long. There are 2^4 = 16 possible opcode patterns. If one opcode bit represents addressing mode and three bits represent the basic operation, the opcode identifies both the operation and the addressing mode.

Operations and interrupts

Basic operations include load, add, subtract, store, conditional and unconditional branching, compare, AND, OR, NOT, XOR, logical shift right, logical shift left and halt. An interrupt signals that the processor must deal with an event requiring an interrupt service routine (ISR). The normal Fetch-Execute cycle is temporarily interrupted. Before the ISR is carried out, the volatile environment must be saved, including information needed to resume the interrupted program correctly. After the ISR, that environment can be restored and execution can continue.

Performance factors

Multiple cores can allow more than one processing activity to take place at the same time. Cache memory provides fast access to data or instructions that the processor needs, reducing the effect of slower access to main memory. A higher clock speed provides more clock cycles in a given time. A larger word length allows the processor to handle more bits in one operation. A wider address bus can represent more addresses, while a wider data bus can transfer more bits at one time.

Common errors

Do not confuse the PC with the MAR: the PC identifies the next instruction, whereas the MAR holds the address currently being accessed. Do not confuse immediate and direct addressing: immediate addressing gives the datum, while direct addressing gives its address. The CIR holds the current instruction, not necessarily the next instruction. A branch changes the normal sequence of instruction addresses, and a compare operation is distinct from an arithmetic subtraction even though both may be used to assess values.