Logic gates study guide

Study sequence

Start with the six required gates and learn their output patterns rather than relying only on names. For each two-input gate, test the four rows in the order 00, 01, 10, 11. This gives a reliable basis for interpreting a circuit. Remember that the two middle rows differ only in which input is 1, while the final row tests the behaviour when both inputs are 1. That final row is especially useful for distinguishing OR from XOR and AND from NAND.

Translating a circuit in both directions

When given a circuit, identify each gate from left to right. Give every intermediate output a temporary name, such as X and Y. Then write the final expression using those names before substituting their definitions. For example, if X = A XOR B and Y = X AND C, the complete expression is (A XOR B) AND C. The parentheses preserve the circuit structure.

When given an expression, work from the innermost operation outward. For (A AND B) OR (NOT C), draw an AND gate for A and B, a NOT gate for C, and an OR gate joining the two results. Check the completed drawing by writing its expression again. If the expression reconstructed from the drawing is different, the circuit is not equivalent to the required expression.

Exam application: circuit truth tables

For a circuit with one or more gates, first count the independent inputs. Two inputs require four rows; three inputs require eight rows. For each row, calculate each gate output in signal order. Do not jump directly to the final column when the circuit contains several stages. If a gate output feeds two later gates, calculate it once and reuse it. After completing the table, inspect selected rows: an AND output should be 1 only when both of its inputs are 1, while a NOT output should always be the opposite of its input.

Reasoning about a half-adder

A half-adder must represent one-bit addition using two outputs. When both inputs are 0, there is no sum and no carry. When exactly one input is 1, the sum is 1 and the carry is 0. When both inputs are 1, the binary result requires a carry, so the sum is 0 and the carry is 1. These three cases show why the sum uses XOR and the carry uses AND. To construct the circuit, connect A and B to both gates, send the XOR output to S, and send the AND output to C.

Tracing a full-adder

A full-adder extends this reasoning by including Cin. Trace the first addition of A and B with a half-adder. Its intermediate sum is then combined with Cin in a second XOR operation to produce the final sum. The carry from the first stage and the carry from the second stage are combined using OR. This gives a structured way to follow the circuit without trying to infer the final output in one step. The key distinction is that a half-adder has no carry input, whereas a full-adder includes one.

Applying the D-type flip-flop

For an edge-triggered D-type flip-flop, focus on the relationship between the data input, the clock edge and the stored output. At the relevant edge, trace the value present at D and identify it as the value stored by the memory unit. Between relevant clock edges, do not assume that changes at D immediately alter the stored output. The specification requires familiarity with its use, not knowledge of its internal operation.

Self-check questions

1. Can you produce the complete truth table for every required gate without confusing XOR and OR?
2. Can you write an expression for a circuit by naming intermediate gate outputs?
3. Can you draw a circuit from an expression while preserving parentheses and operation order?
4. Can you complete a multi-stage truth table using intermediate columns?
5. Can you explain why a half-adder needs XOR for sum and AND for carry?
6. Can you trace the additional carry input in a full-adder?
7. Can you describe what an edge-triggered D-type flip-flop is used for without explaining its internal operation?

For final checking, compare a circuit's truth table with the table obtained from its Boolean expression. Equivalent circuits must give the same final output for every input combination.